At Brioconcept, simulation is in our DNA.  Our standard design flow includes simulation  in order to provide a robust design on the first revision.  The qualification in lab is to confirm our simulation results.


➣ FPGA Serdes simulation

➣ Pre-layout simulation

➣ Post-layout simulation

➣ Clock and critical nets

➣ Board spice creation

➣ Ground & supplies bounce

➣ Power planes resonance analysis

➣ Geometries optimization

➣ Differential vias (>20Ghz)

➣ Focused crosstalk on critical section

➣ Entire board crosstalk

➣ High speed optimization

➣ Cost reduction



➣ Mentor Graphics® HyperLynx®

➣ Matlab

➣ SPICE simulator

Related Projects